Method of forming a field effect transistor having a gate structure with a first section having a first effective work function above a center portion of the channel region and with second sections having a second effective work function above opposing sidewalls of the channel region

ABSTRACT

In view of the foregoing, disclosed herein are embodiments of an improved field effect transistor (FET) structure and a method of forming the structure. The FET structure embodiments each incorporate a unique gate structure. Specifically, this gate structure has a first section above a center portion of the FET channel region and second sections above the channel width edges (i.e., above the interfaces between the channel region and adjacent isolation regions). The first and second sections differ (i.e., they have different gate dielectric layers and/or different gate conductor layers) such that they have different effective work functions (i.e., a first and second effective work-function, respectively). The different effective work functions are selected to ensure that the threshold voltage at the channel width edges is elevated.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.13/535,394, filed Jun. 28, 2012, which is a divisional of U.S. patentapplication Ser. No. 12/194,039, filed Aug. 19, 2008, issued as U.S.Pat. No. 8,237,233 on Aug. 7, 2012, the complete disclosure of which isincorporated herein by reference.

BACKGROUND

1. Field of the Invention

The embodiments of the invention generally relate to complementary metaloxide semiconductor body (CMOS) devices and, more specifically, to aCMOS structure and method of forming the CMOS structure with dual metalgates to suppress corner leakage.

2. Description of the Related Art

As complementary metal oxide semiconductor (CMOS) devices are scaled insize, conventional gate stack structures are being replaced by metalgate stack structures. Specifically, a conventional gate stack structuretypically includes a thin silicon oxide (SiO₂) gate dielectric layer anda doped-polysilicon gate conductor layer. Unfortunately, dopedpolysilicon gate conductor layers are subject to depletion effects.These depletion effects result in an increase in the effective gatedielectric layer thickness and, thereby limit device scaling. Thus, highk dielectric layer-metal gate conductor layer stacks with different workfunctions for N-type field effect transistors (NFETs) and p-type fieldeffect transistors, have been introduced. These stacks are improvementsover the conventional gate structures in that the high k-dielectriclayer minimizes leakage current and the metal gate conductor layer isnot subject to depletion effects. However, with ever narrower channelwidths new concerns for future CMOS technology generations and, moreparticularly, for CMOS technology generations at or beyond the 65 nmnode are introduced even with such high-k dielectric layer-metal gateconductor layer stacks.

SUMMARY

One embodiment of the field effect transistor of the present inventioncomprises a substrate. A semiconductor body is positioned on thesubstrate. This semiconductor body comprises a channel region with asidewall and a center portion. An isolation region is also on thesubstrate positioned laterally adjacent to the sidewall. A gatestructure traverses the width of the channel region and further extendslaterally beyond the sidewall onto the isolation region. This gatestructure comprises a first section on the semiconductor body above thecenter portion of the channel region and a second section above thesemiconductor body sidewall (i.e., above the interface between thesemiconductor body and the isolation region). This second section isdifferent from the first section. Specifically, the first and secondsections differ such that they have different effective work functions(i.e., a first and second effective work-function, respectively). Forexample, the first section can have a first gate conductor layer and thesecond section can have a second gate conductor layer that is differentfrom the first gate conductor layer and, more particularly, that has adifferent work function than the first gate conductor layer.Alternatively, the first section can have a first gate dielectric layerand the second section can have a second gate dielectric layer that isdifferent from the first gate dielectric layer and, particularly, thathas a different fixed charge content than the first gate dielectriclayer, thereby resulting in different effective work functions in thefirst and second sections.

Another embodiment of the field effect transistor of the presentinvention comprises a substrate. A semiconductor body is positioned onthe substrate. This semiconductor body comprises a channel region with asidewall and a center portion. An isolation region is also on thesubstrate positioned laterally adjacent to the sidewall. A gatestructure traverses the width of the channel region and further extendslaterally beyond the sidewall onto the isolation region. This gatestructure comprises a first section on the semiconductor body above thecenter portion of the channel region and a second section above thesemiconductor body sidewall (i.e., above the interface between thesemiconductor body and the isolation region). This second section isdifferent from the first section. Specifically, in this embodiment thefirst and second sections have both different gate dielectric layers anddifferent gate conductor layers such that the first section has a firsteffective work-function and the second section has a second effectivework function that is different from the first effective work-function.

One embodiment of the field effect transistor formation method of thepresent invention comprises providing a substrate. On that substrate, asemiconductor body is formed. Additionally, an isolation region isformed on the substrate such that it is positioned laterally adjacent toa sidewall of the semiconductor body. Next, a gate structure is formedsuch that it traverses the width of a channel region of thesemiconductor body and further such that it extends laterally beyond thesidewall of the semiconductor body onto the isolation region. This gatestructure is specifically formed with a first section, having a firsteffective work-function, above a center portion of the channel regionand with a second section, having a second effective work functiondifferent from the first effective work-function, above the sidewall(i.e., above the interface between the isolation region and thesemiconductor body). This process of forming the gate structure can, forexample, comprise forming the first section with a first gate conductorlayer and the second section with a second gate conductor layer that isdifferent from the first gate conductor layer (i.e., that has adifferent work function than the first gate conductor layer).Alternatively, this process of forming the gate structure can compriseforming the first section with a first gate dielectric layer and thesecond section can have a second gate dielectric layer that is differentfrom the first gate dielectric layer and, particularly, that has adifferent fixed charge content than the first gate dielectric layer sothat the resulting first and second sections have different effectivework functions.

Another embodiment of the field effect transistor formation method ofthe present invention comprises providing a substrate. On thatsubstrate, a semiconductor body is formed. Additionally, an isolationregion is formed on the substrate such that it is positioned laterallyadjacent to a sidewall of the semiconductor body. Next, a gate structureis formed such that it traverses the width of a channel region of thesemiconductor body and further such that it extends laterally beyond thesidewall of the semiconductor body onto the isolation region. This gatestructure is specifically formed with a first section, having a firsteffective work-function, above a center portion of the channel regionand with a second section, having a second effective work functiondifferent from the first effective work-function, above the sidewall(i.e., above the interface between the isolation region and thesemiconductor body). In this embodiment, the process of forming the gatestructure can, for example, comprise forming the first and secondsections with both different gate dielectric layers and different gateconductor layers.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

The embodiments of the invention will be better understood from thefollowing detailed description with reference to the drawings, which arenot necessarily drawing to scale and in which:

FIG. 1 is a top view diagram illustrating the embodiments 100 a-c of thefield effect transistor;

FIG. 2 is a cross-section diagram illustrating one embodiment 100 a ofthe field effect transistor;

FIG. 3 is a cross-section diagram illustrating another embodiment 100 bof the field effect transistor;

FIG. 4 is a cross-section diagram illustrating yet another embodiment100 c of the field effect transistor;

FIG. 5 is a flow diagram illustrating the embodiments of the method ofthe present invention;

FIG. 6 is a cross-section diagram illustrating a partially completedfield effect transistor, as illustrated in FIGS. 1-4;

FIG. 7 is a cross-section diagram illustrating a partially completedfield effect transistor, as illustrated in FIGS. 1-4;

FIG. 8 is a cross-section diagram illustrating a partially completedfield effect transistor, as illustrated in FIG. 2 and FIG. 4;

FIG. 9 is a cross-section diagram illustrating a partially completedfield effect transistor, as illustrated in FIG. 2 and FIG. 4;

FIG. 10 is a cross-section diagram illustrating a partially completedfield effect transistor, as illustrated in FIG. 3;

FIG. 11 is a cross-section diagram illustrating a partially completedfield effect transistor, as illustrated in FIG. 3; and

FIG. 12 is a cross-section diagram illustrating a partially completedfield effect transistor, as illustrated in FIG. 3.

DETAILED DESCRIPTION

The embodiments of the invention and the various features andadvantageous details thereof are explained more fully with reference tothe non-limiting embodiments that are illustrated in the accompanyingdrawings and detailed in the following description.

As mentioned above, complementary metal oxide semiconductor body (CMOS)devices are scaled in size, conventional gate stack structures are beingreplaced by metal gate stack structures. Specifically, a conventionalgate stack structure typically includes a thin silicon oxide (SiO₂) gatedielectric layer and a doped-polysilicon gate conductor layer.Unfortunately, doped polysilicon gate conductor layers are subject todepletion effects. These depletion effects result in an increase in theeffective gate dielectric layer thickness and, thereby limit devicescaling. Thus, high k dielectric layer-metal gate conductor layer stackshave been introduced. These stacks are improvements over theconventional gate structures in that the high k-dielectric layerminimizes leakage current and the metal gate conductor layer is notsubject to depletion effects. However, with ever narrower channel widthsnew concerns for future CMOS technology generations and, moreparticularly, for CMOS technology generations at or beyond the 65 nmnode are introduced even with such high-k dielectric layer-metal gateconductor layer stacks. Specifically, narrow channel width edge effects(e.g., decreases in threshold voltage (Vt) at the channel regionsidewalls relative to the center portion of the channel region and alsocorner parasitic currents) can degrade power-performance optimization oftechnologies. Therefore, there is a need in the art for a field effecttransistor (FET) structure that compensates for such narrow channelwidth edge effects and, more particularly, a FET structure that elevatesthe threshold voltage at the channel width edges and prevents currentleakage.

In view of the foregoing, disclosed herein are embodiments of animproved field effect transistor (FET) structure and a method of formingthe structure. The FET structure embodiments each incorporate a uniquegate structure. Specifically, this gate structure has a first sectionabove a center portion of the FET channel region and second sectionsabove the channel width edges (i.e., above the interfaces between thechannel region and adjacent isolation regions). The first and secondsections differ (i.e., they have different gate dielectric layers and/ordifferent gate conductor layers) such that they have different effectivework functions (i.e., a first and second effective work-function,respectively). The different effective work functions are selected toensure that the threshold voltage at the channel width edges iselevated.

More particularly, referring to FIG. 1, each of the embodiments of thefield effect transistor 100 a-c of the present invention comprises asubstrate 101. The substrate 101 can, for example, comprise bulk siliconwafer or silicon-on-insulator (SOI) wafer. A semiconductor body 110(e.g., a patterned single crystalline silicon layer) can be positionedon the substrate 101. This semiconductor body 110 can comprisesource/drain regions 160 and a channel region 150 between thesource/drain regions 160. The channel region 150 can have sidewalls 152and a center portion 151. Isolation regions 120 can also be positionedon the substrate 101. Specifically, these isolation regions 120 can bepositioned laterally immediately adjacent to the semiconductor body 110and, more particularly, immediately adjacent to the sidewalls 152 of thesemiconductor body channel region 150. The isolation regions 120 can,for example, comprise shallow trench isolation (STI) regions filled withsuitable isolation material(s) (e.g., SiO₂).

A gate structure (200, 300 or 400, depending upon the embodiment)traverses the width 180 of the channel region 150 and further extendslaterally beyond the sidewalls 152 onto the isolation regions 120. Thisgate structure 200, 300, 400 comprises a first section 171 on thesemiconductor body 110 above the center portion 151 of the channelregion 150 and second sections 172 above the semiconductor bodysidewalls 152 (i.e., above the interfaces between the semiconductor body110 and the isolation regions 120). The different embodiments of thefield effect transistor of the present invention vary with respect tothis gate structure (e.g., see gate structure 200 of FIG. 2, gatestructure 300 in FIG. 3 and the gate structure 400 in FIG. 4). However,in each of the embodiments, the second sections 172 are different fromthe first section 171. Specifically, the first and second sections171-172 are configured differently such that they have differenteffective work functions (i.e., a first and second effectivework-function, respectively) in order to ensure that the thresholdvoltage of the channel region 150 at the sidewalls 152 (i.e., at thechannel width edges) is at least equal to threshold voltage at thecenter portion 151 of the channel region 150. The different effectivework functions are accomplished through the use of different gateconductor layers and/or different gate dielectric layers in thedifferent sections 171-172.

Referring to FIG. 2 in combination with FIG. 1, in one embodiment 100 athe gate structure 200 comprises a single gate dielectric layer 211 thattraverses the width 180 of the channel region 150 of the semiconductorbody 110. This gate dielectric layer 211 further extends laterallybeyond the channel region sidewalls 152 onto the isolation regions 120.Thus, both the first and second sections 171 and 172 of the gatestructure comprise the same gate dielectric layer 211. This gatedielectric layer 211 can comprise a high-k dielectric material.

The first section 171 can further comprise a first gate conductor layer221 on the gate dielectric layer 211 above the center portion 151 of thechannel region 150. The second sections 172 can each further comprise asecond gate conductor layer 222 on the gate dielectric layer 211 above acorresponding sidewall 152. The first gate conductor layer 221 and thesecond gate conductor layer 222 comprise different conductive materialswith different work functions.

For example, the first gate conductor layer 221 can comprise a firstmetal and the second gate conductor layer 222 can comprise a secondmetal that is different from the first metal and, more particularly,that has a different work function from the first metal. Given theformation techniques, discussed in detail below, the first gateconductor layer 221 can further comprise a layer of the second metalabove the first metal. Those skilled in the art will recognize that theeffective work function of this first gate conductor layer 221 will bedetermined largely based on the first metal closest to the gatedielectric layer 211. In the case of an n-type field effect transistor(NFET), the first metal of the first gate conductor layer 221 cancomprise an n-type metal or n-type metal alloy and the second metal ofthe second gate conductor layer 222 can comprise a p-type metal orp-type metal alloy. In the case of a p-type field effect transistor(PFET), the first metal of the first gate conductor layer 221 cancomprise a p-type metal or p-type metal alloy and the second metal ofthe second gate conductor layer 222 can comprise an n-type metal orn-type metal alloy.

In another example, the first gate conductor layer 221 can comprise ametal and the second gate conductor layer 222 can comprise a dopedpolysilicon that has a different work function than the metal. Again,given the formation techniques, discussed in detail below, the firstgate conductor layer 221 can further comprise a layer of the dopedpolysilicon above metal. Those skilled in the art will recognize thatthe effective work function of this first gate conductor layer 221 willbe determined largely based on the metal closest to the gate dielectriclayer 211. In the case of an NFET, the metal of the first gate conductorlayer 221 can comprise an n-type metal or n-type metal alloy and thepolysilicon of the second gate conductor layer 222 can be doped with ap-type dopant (e.g., boron (B)). In the case of a p-type field effecttransistor (PFET), the metal of the first gate conductor layer 221 cancomprise a p-type metal or p-type metal alloy and the polysilicon of thesecond gate conductor layer 222 can be doped with an n-type dopant(e.g., phosphorous, antimony or arsenic).

Referring to FIG. 3 in combination with FIG. 1, in another embodiment100 b the first section 171 of the gate structure 300 comprise a firstgate dielectric layer 311 on the semiconductor body 110 only above thecenter portion 151 of the channel region 150. The second sections 171 ofthe gate structure 300 each comprise a second gate dielectric layer 312above a corresponding sidewall 152. That is, in a given second section172, the second gate dielectric layer 312 is positioned above thechannel sidewall 152 (i.e., above the semiconductor body 110-isolationregion 120 interface) such that is positioned on both the isolationregion 120 and edge portions of the channel region 150. These first andsecond gate dielectric layers 311-312 can be different gate dielectricmaterials with different fixed charge contents and, optionally, can havedifferent gate dielectric layer thicknesses, thereby resulting indifferent effective work functions in the first and second sections171-172. For example, the first gate dielectric layer 311 can comprise afirst high-k dielectric material and the second gate dielectric layer312 can comprise a second high-k dielectric material different from thefirst high-k dielectric material and having a different fixed chargedcontent than the first high-k dielectric material. Additionally, thefirst gate dielectric layer 311 can have a first thickness and thesecond gate dielectric layer 312 can have a second thickness that isdifferent from the first thickness (e.g., that is greater than the firstthickness, as illustrated).

The gate structure 300 can further comprise a single metal gateconductor layer 321 that is positioned above the first gate dielectriclayer 311 traversing the width 180 of the channel region 150 of thesemiconductor body 110 and that is further positioned above the secondgate dielectric layer 312 extending laterally beyond the channel regionsidewalls 152 above the isolation regions 120. In the case of an NFET,the metal of this single gate conductor layer 321 can comprise an n-typemetal or n-type metal alloy, whereas in the case of PFET, the metal ofthis single gate conductor layer 321 can comprise a p-type metal orp-type metal alloy.

Referring to FIG. 4, in yet another embodiment 100 c, the first section171 of the gate structure 400 can comprise a first gate dielectric layer411 above the center portion 151 of the channel region 150 and a firstgate conductor layer 421 on the first gate dielectric layer 411. Thesecond sections 172 of the gate structure 400 can each comprise a secondgate dielectric layer 412 above a corresponding sidewall 152 and asecond gate conductor layer 422 above the second gate dielectric layer412.

In this embodiment 100 c as with the first embodiment 100 a illustratedin FIG. 2, the first gate conductor layer 421 and the second gateconductor layer 422 can comprise different conductive materials thathave different work functions.

For example, the first gate conductor layer 421 can comprise a firstmetal and the second gate conductor layer 422 can comprise a secondmetal that is different from the first metal and, more particularly,that has a different work function from the first metal. Given theformation techniques, discussed in detail below, the first gateconductor layer 421 can further comprise a layer of the second metalabove the first metal. Those skilled in the art will recognize that theeffective work function of this first gate conductor layer 421 will bedetermined largely based on the first metal closest to the gatedielectric layer 411. In the case of an n-type field effect transistor(NFET), the first metal of this first gate conductor layer 421 cancomprise an n-type metal or n-type metal alloy and the second metal ofthe second gate conductor layer 422 can comprise a p-type metal orp-type metal alloy. In the case of a p-type field effect transistor(PFET), the first metal of the first gate conductor layer 421 cancomprise a p-type metal or p-type metal alloy and the second metal ofthe second gate conductor layer 422 can comprise an n-type metal orn-type metal alloy.

In another example, the first gate conductor layer 421 can comprise ametal and the second gate conductor layer 422 can comprise a dopedpolysilicon that has a different work function than the metal. Given theformation techniques, discussed in detail below, the first gateconductor layer 421 can further comprise a layer of doped polysiliconabove the metal. Those skilled in the art will recognize that theeffective work function of this first gate conductor layer 421 will bedetermined largely based on the metal closest to the gate dielectriclayer 411. In the case of an NFET, the metal of the first gate conductorlayer 421 can comprise an n-type metal or n-type metal alloy and thepolysilicon of the second gate conductor layer 422 can be doped with ap-type dopant (e.g., boron (B)). In the case of a p-type field effecttransistor (PFET), the metal of the first gate conductor layer 421 cancomprise a p-type metal or p-type metal alloy and the polysilicon of thesecond gate conductor layer 422 can be doped with an n-type dopant(e.g., phosphorous, antimony or arsenic).

Additionally, in this embodiment 100 c the first gate dielectric layer411 and the second gate dielectric layer 412 comprise differentdielectric materials with different fixed charge contents and,optionally, with different thicknesses, resulting in different effectivework functions. For example, the first gate dielectric layer 411 cancomprise a first high-k dielectric material and the second gatedielectric layer 412 can comprise a second high-k dielectric materialdifferent from the first high-k dielectric material and having differentfixed charge content than the first high-k dielectric material.Additionally, the first gate dielectric layer 411 can have a firstthickness and the second gate dielectric layer 412 can have a secondthickness that is different from the first thickness (e.g., that isgreater than the first thickness, as illustrated). It should be notedthat given the formation techniques, described in detail below, thesecond gate dielectric layer 412 can further comprise a layer of thefirst high-k dielectric material below the second high-k dielectricmaterial. That is, the first high-k dielectric material of the firstgate dielectric layer 411 can extend laterally beyond the sidewalls 152onto the isolation region 120 and the second high-k dielectric materialcan be formed above. Thus, the second gate dielectric layer 412 cancomprise several layers of different types of high-k dielectrics.

Referring to FIG. 5, also disclosed are method embodiments for formingthe above-described field effect transistor embodiments. The methodembodiments comprise providing a substrate 101, such as a bulk siliconor silicon-on-insulator (SOI) wafer (502, see FIG. 6).

Then, a semiconductor body 110 and isolation regions 120 are formed onthe substrate 101 such that the isolation regions 120 are positionedlaterally adjacent to the sidewalls 152 of the semiconductor body 110(504, see FIG. 7). For example, shallow trench isolation (STI) regions120 can be formed in the semiconductor material 103 (e.g., singlecrystalline silicon) at the top surface of the substrate 101, usingconventional STI processing techniques, such that a remaining portion ofthe semiconductor material 103 creates the semiconductor body 110.

Next, a gate structure 200, 300, 400 is formed that traverses the width180 of a designated channel region 150 of the semiconductor body 110 andfurther that extends laterally beyond the sidewalls 152 onto theisolation regions 120 (506, see FIG. 1). This gate structure 200, 300,400 is specifically formed with a first section 171, having a firsteffective work-function, above a center portion 151 of the channelregion 150 and with a second section 172, having a second effective workfunction different from the first effective work-function, above thesidewalls 152 in the channel region 150 (i.e., above the channel widthedges at the interface between the semiconductor body 110 and theisolation regions 120). The first effective work-function of the firstsection 171 and the different second effective work function of thesecond section 172 ensure that the threshold voltage of the channelregion 150 at the sidewalls 152 (and particularly at the channel widthcorners) is at least equal to the threshold voltage in the centerportion 151 of the channel region 150. To accomplish this severaldifferent method embodiments are disclosed.

In one embodiment of the method, a gate dielectric layer 211 is formedthat traverses the width 180 of the designated channel region 150 andfurther extends laterally beyond the channel sidewalls 152 onto theisolation regions 120 (602, see FIG. 8). Specifically, a high-kdielectric material can be deposited over the semiconductor body 110 andisolation regions 120. Then, a first gate conductor layer 221 is formedon the gate dielectric layer 211 and, more particularly, just above thecenter portion 151 of the channel region 150 (604, see FIG. 9). Next, asecond gate conductor layer 222, which is different from the first gateconductor layer 221, is formed on the gate dielectric layer 211 abovethe channel sidewalls 152 (606, see FIG. 2).

Specifically, the processes 604-606 can comprise depositing a metal ontothe gate dielectric layer 211. In the case of an NFET, this metal cancomprise an n-type metal or n-type metal alloy, whereas in the case ofPFET, this metal can comprise a p-type metal or p-type metal alloy. Thismetal is then lithographically patterned such that is remains only abovethe channel center portion 151 (see item 221 of FIG. 9). Next, a secondmetal, which has a different work function than the first metal, isdeposited. For example, in the case of an NFET, this second metal cancomprise a p-type metal or p-type metal alloy, whereas in the case ofPFET, this second metal can comprise an n-type metal or n-type metalalloy (as discussed above). Alternatively, instead of depositing asecond metal, a polysilicon material can be deposited. This polysiliconmaterial can be either appropriately doped at deposition or subsequentlyimplanted with appropriate dopants such that it has a different workfunction than the previously deposited metal. For example, in the caseof an NFET, this polysilicon can be doped with a p-type dopant (e.g.,boron (B)), whereas in the case of PFET, this polysilicon can be dopedwith an n-type dopant (e.g., phosphorous (P), arsenic (As) or antimony(Sb)). The second metal (or doped polysilicon) is then lithographicallypatterned such that it traverses the metal above the channel centerportion 151 and further such that it extends laterally beyond thechannel sidewalls 152 onto the portion of the gate dielectric layer 211exposed above the isolation regions 120 (see item 222 in FIG. 2).

In another embodiment of the method, a first gate dielectric layer 311is formed above the center portion 151 of the channel region 150 only(702, see FIG. 10). Next, a second gate dielectric layer 312 is formedabove the channel sidewalls 152 adjacent to the first gate dielectriclayer 311 (704, see FIG. 11). This second gate dielectric layer 312 isdifferent from the first gate dielectric layer 311 and, moreparticularly, has a different fixed charge content than the first gatedielectric layer 311.

Specifically, the processes 702-704 can comprise depositing a firsthigh-k dielectric material. Next, that first high-k dielectric materialis lithographically patterned such that portions above the channelsidewalls 152 are removed (see item 311 in FIG. 10). Then, a secondhigh-k dielectric material that is different from the first high-kmaterial (with a different charge content) is deposited andlithographically patterned such that a portion of this second high-kdielectric material above the channel center portion 151 is removed (seeitem 312 in FIG. 11). Since the first and second dielectric materialsare different and deposited separately, they can also be deposited suchthat they have different thicknesses (as illustrated), if necessary, toachieve the desired different effective work functions.

Once the first and second gate dielectric layers 311, 312 are formed atprocess 702-704, a gate conductor layer 321 is formed on both the firstgate dielectric layer 311 and on the second gate dielectric layer 312(706, see FIG. 3). This gate conductor layer 321 can be formed bydepositing and, then, lithographically patterning a metal. In the caseof an NFET, this metal can comprise an n-type metal or n-type metalalloy, whereas in the case of PFET, this metal can comprise a p-typemetal or p-type metal alloy.

In another embodiment of the method, a first gate dielectric layer 411is formed that traverses the width 180 of the designated channel region150 and further extends laterally beyond the channel sidewalls 152 ontothe isolation regions 120 (802, see FIG. 8). Then, a first gateconductor layer 421 is formed on the first gate dielectric layer 411and, more particularly, just above the center portion 151 of the channelregion 150 (804, see FIG. 9). Next, a second gate dielectric layer 412different from the first gate dielectric layer 411 (i.e., with adifferent charge content) is formed on the first gate dielectric layer411 above the channel sidewalls 152 (806, see FIG. 12). Finally, asecond gate conductor layer 422 different from the first gate conductorlayer 421 is formed on the second gate dielectric layer 412 above thechannel sidewalls 152 (808, see FIG. 4).

Specifically, the process 802-808 can comprise depositing a first high-kdielectric material that traverses the width 180 of the designatedchannel region 150 and further extends laterally beyond the channelsidewalls 152 onto the isolation regions 120 (see item 411 of FIG. 8).Next, a metal can be deposited onto the first high-k dielectricmaterial. In the case of an NFET, this metal can comprise an n-typemetal or n-type metal alloy, whereas in the case of PFET, this metal cancomprise a p-type metal or p-type metal alloy. This metal is thenlithographically patterned such that is remains only above the channelcenter portion 151, exposing the first high-k dielectric material abovethe channel sidewalls 152 (see item 421 of FIG. 9). Then, a secondhigh-k dielectric material that is different from the first high-kdielectric material (i.e., that has a different charge content) can bedeposited across the exposed first high-k dielectric layer 411 and themetal 421. A portion of the second high-k dielectric material on thepreviously deposited metal 421 above the channel center portion 151 isremoved (i.e., the second high-k dielectric material is lithographicallypatterned) (see item 412 of FIG. 12). Finally, a second metal, which hasa different work function than the previously deposited first metal, isdeposited. For example, in the case of an NFET, this second metal cancomprise a p-type metal or p-type metal alloy, whereas in the case ofPFET, this second metal can comprise an n-type metal or n-type metalalloy (as discussed above). Alternatively, instead of depositing asecond metal, a polysilicon material can be deposited. This polysiliconmaterial can be either appropriately doped at deposition or subsequentlyimplanted with appropriate dopants such that it has a different workfunction than the previously deposited metal. For example, in the caseof an NFET, this polysilicon can be doped with a p-type dopant (e.g.,boron (B)), whereas in the case of PFET, this polysilicon can be dopedwith an n-type dopant (e.g., phosphorous (P), arsenic (As) or antimony(Sb)). The second metal (or doped polysilicon) is then lithographicallypatterned such that it traverses the metal 421 above the channel centerportion 151 and further such that it extends laterally beyond thechannel sidewalls 152 onto the portion of the gate dielectric layer 211exposed above the isolation regions 120 (see item 422 of FIG. 4).

Referring again to FIG. 5, after completion of the gate structure 200,300 or 400 additional processing is performed in order to complete theFET structure. This additional processing includes, but is not limitedto, halo implantation, source/drain extension implantation, gatesidewall spacer formation, source/drain implantation, silicideformation, interlayer dielectric deposition, contact formation, etc.

It should be noted that for the purposes of this disclosure n-typemetals or metal alloys are defined as near conduction band metals ormetal alloys (e.g., metals or metal alloys within 0.2 eV of the E_(c) ofthe semiconductor body 110). Exemplary n-type metals or metal alloysinclude, but are not limited to, titanium nitride, titanium siliconnitride, tantalum nitride, tantalum silicon nitride, aluminum, silver,hafnium, etc. Contrarily, p-type metals or metal alloys are defined asnear valence band metals or metal alloys (e.g., metals or metal alloyswithin 0.2 eV of the E_(v) of the semiconductor body 110). Exemplaryp-type metals or metal alloys include, but are not limited to, rhenium,rhenium oxide, platinum, ruthenium, ruthenium oxide, nickel, palladium,iridium, etc. It should further be understood that high-k dielectricmaterials comprise dielectric materials having a dielectric constant “k”above 3.9 (i.e., above the dielectric constant of SiO₂). Exemplaryhigh-k dielectric materials include, but are not limited to,hafnium-based materials (e.g., HfO₂, HfSiO, HfSiON, or HfAlO) or someother suitable high-k dielectric material (e.g., Al₂O₃, TaO₅, ZrO₅,etc.).

Furthermore, it should be understood that the corresponding structures,materials, acts, and equivalents of all means or step plus functionelements in the claims below are intended to include any structure,material, or act for performing the function in combination with otherclaimed elements as specifically claimed. Additionally, it should beunderstood that the above-description of the present invention has beenpresented for purposes of illustration and description, but is notintended to be exhaustive or limited to the invention in the formdisclosed. Many modifications and variations will be apparent to thoseof ordinary skill in the art without departing from the scope and spiritof the invention. The embodiments were chosen and described in order tobest explain the principles of the invention and the practicalapplication, and to enable others of ordinary skill in the art tounderstand the invention for various embodiments with variousmodifications as are suited to the particular use contemplated.Well-known components and processing techniques are omitted in theabove-description so as to not unnecessarily obscure the embodiments ofthe invention.

It should also be understood that the terminology used in theabove-description is for the purpose of describing particularembodiments only and is not intended to be limiting of the invention.For example, as used herein, the singular forms “a”, “an” and “the” areintended to include the plural forms as well, unless the context clearlyindicates otherwise. Furthermore, as used herein, the terms “comprises”,“comprising,” and/or “incorporating” when used in this specification,specify the presence of stated features, integers, steps, operations,elements, and/or components, but do not preclude the presence oraddition of one or more other features, integers, steps, operations,elements, components, and/or groups thereof.

Therefore, disclosed above are embodiments of an improved field effecttransistor (FET) structure and a method of forming the structure. TheFET structure embodiments each incorporate a unique gate structure.Specifically, this gate structure has a first section above a centerportion of the FET channel region and second sections above the channelwidth edges (i.e., above the interfaces between the channel region andadjacent isolation regions). The first and second sections differ (i.e.,they have different gate dielectric layers and/or different gateconductor layers) such that they have different effective work functions(i.e., a first and second effective work-function, respectively). Thedifferent effective work functions are selected to ensure that thethreshold voltage at the channel width edges is elevated.

What is claimed is:
 1. A field effect transistor comprising: asubstrate; a semiconductor body on said substrate, said semiconductorbody comprising a channel region having sidewalls, edge portions at saidsidewalls and a center portion positioned laterally between said edgeportions; an isolation region on said substrate positioned laterallyadjacent to said sidewalls; and a gate structure traversing a width ofsaid channel region and further extending laterally beyond saidsidewalls onto said isolation region, said gate structure comprising afirst section above said center portion and second sections differentfrom said first section above said edge portions and extending laterallybeyond said sidewalls onto said isolation region, and said first sectioncomprising a first gate dielectric layer above said center portion, saidsecond sections each comprising a second gate dielectric layer above anedge portion of said channel region and extending laterally beyond asidewall of said channel region onto said isolation region, and saidfirst gate dielectric layer and said second gate dielectric layercomprising different gate dielectric materials with different fixedcharge contents such that said first section has a first effectivework-function and said second section has a second effective workfunction that is different from said first effective work-function. 2.The field effect transistor of claim 1, said first section having saidfirst effective work-function and said second section having said secondeffective work function such that a second threshold voltage at saidsidewall is at least equal to a first threshold voltage at said centerportion.
 3. The field effect transistor of claim 1, said gate structurefurther comprising a single gate conductor layer on said first gatedielectric layer in said first section and extending laterally over saidsecond gate dielectric layer in said second sections, said single gatedielectric layer has different thicknesses in said first section andsaid second sections.
 4. The field effect transistor of claim 3, saidsingle gate conductor layer comprising any one of a metal and a dopedpolysilicon.
 5. The field effect transistor of claim 1, said first gatedielectric layer comprising a first high-k dielectric material and saidsecond gate dielectric layer comprising a second high-k dielectricmaterial different from said first high-k dielectric material.
 6. Thefield effect transistor of claim 1, said first gate dielectric layer andsaid second gate dielectric layer having different thicknesses.
 7. Afield effect transistor comprising: a substrate; a semiconductor body onsaid substrate, said semiconductor body comprising a channel regionhaving sidewalls, edge portions at said sidewalls and a center portionpositioned laterally between said edge portions; an isolation region onsaid substrate positioned laterally adjacent to said sidewalls; and agate structure traversing a width of said channel region and furtherextending laterally beyond said sidewalls onto said isolation region,said gate structure comprising a first section above said center portionand second sections different from said first section above said edgeportions and extending laterally beyond said sidewalls onto saidisolation region, and said first section comprising a first gatedielectric layer above said center portion, said second sections eachcomprising a second gate dielectric layer above an edge portion of saidchannel region and extending laterally beyond a sidewall of said channelregion onto said isolation region and further onto an end of said firstgate dielectric layer in said first section, and said first gatedielectric layer and said second gate dielectric layer comprisingdifferent gate dielectric materials with different fixed charge contentssuch that said first section has a first effective work-function andsaid second section has a second effective work function that isdifferent from said first effective work-function.
 8. The field effecttransistor of claim 8, said first section having said first effectivework-function and said second section having said second effective workfunction such that a second threshold voltage at said sidewall is atleast equal to a first threshold voltage at said center portion.
 9. Thefield effect transistor of claim 8, said gate structure furthercomprising a single gate conductor layer on said first gate dielectriclayer in said first section and extending laterally over said secondgate dielectric layer in said second sections, said single gatedielectric layer has different thicknesses in said first section andsaid second sections.
 10. The field effect transistor of claim 9, saidsingle gate conductor layer comprising any one of a metal and a dopedpolysilicon.
 11. The field effect transistor of claim 8, said first gatedielectric layer comprising a first high-k dielectric material and saidsecond gate dielectric layer comprising a second high-k dielectricmaterial different from said first high-k dielectric material.
 12. Thefield effect transistor of claim 8, said first gate dielectric layer andsaid second gate dielectric layer having different thicknesses.
 13. Thefield effect transistor of claim 8, said first gate dielectric layerbeing relatively thin as compared to said second gate dielectric layer.14. A method of forming a field effect transistor, said methodcomprising: providing a substrate; forming, on said substrate, asemiconductor body and an isolation region positioned laterally aroundsaid semiconductor body; and forming a gate structure traversing a widthof a channel region in said semiconductor body, said channel regionhaving sidewalls adjacent to said isolation region, edge portions atsaid sidewalls and a center portion positioned laterally between saidedge portions, said forming of said gate structure comprising formingsaid gate structure such that said gate structure comprises a firstsection above said center portion and second sections different fromsaid first section above said edge portions and extending laterallybeyond said sidewalls onto said isolation region, said first sectioncomprising a first gate dielectric layer above said center portion, saidsecond sections each comprising a second gate dielectric layer above anedge portion of said channel region and extending laterally beyond asidewall of said channel region onto said isolation region, and saidfirst gate dielectric layer and said second gate dielectric layercomprising different gate dielectric materials with different fixedcharge contents such that said first section has a first effectivework-function and said second section has a second effective workfunction that is different from said first effective work-function. 15.The method of claim 14, said forming of said gate structure furthercomprising: depositing said first gate dielectric layer over saidchannel region and said isolation region; lithographically patterningsaid first gate dielectric layer such that said isolation region andsaid edge portions of said channel region are exposed and said firstgate dielectric layer remains on said center portion only of saidchannel region; depositing said second gate dielectric layer on saidfirst gate dielectric layer and extending laterally over said edgeportions of said channel region and onto said isolation region;lithographically patterning said second gate dielectric layer to exposesaid first gate dielectric layer above said center portion of saidchannel region.
 16. The method of claim 15, said lithographicallypatterning of said second gate dielectric layer being performed so thatsaid second gate dielectric layer on each edge portion of said channelregion further extends laterally over an end of said first gatedielectric layer.
 17. The method of claim 15, said forming of said gatestructure further comprising forming a single gate conductor layer onsaid first gate dielectric layer in said first section and extendinglaterally over said second gate dielectric layer in said secondsections.
 18. The method of claim 15, said first gate dielectric layercomprising a first high-k dielectric material and said second gatedielectric layer comprising a second high-k dielectric materialdifferent from said first high-k dielectric material.
 19. The method ofclaim 15, said first gate dielectric layer and said second gatedielectric layer being deposited so as to have different thicknesses.20. The method of claim 15, said first gate dielectric layer and saidsecond gate dielectric layer being deposited such that said firstdielectric layer is relatively thin as compared to said second gatedielectric layer.